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A clock gated flip-flop for low power applications

Rajesh Naik.B

A clock gated flip-flop for low power applications Rajesh Naik.B - IIITDM Kancheepuram Dept of Electronics Engineering 2012

B.Tech - Theses

Subjects--Index Terms: Flip-flop, Low power

Dewey Class. No.: 004.312.42 RAJ

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