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Enabling in memory computing with energy efficient memory architecture for AI hardware accelerators

By:

Kavitha S

Contributor(s):

Kavitha S [Dr. bhupendra S reniwal and Prof. binsu j kailath]

Publication details: Chennai ECE 2025Subject(s):

Static random access memory; in memory computing; arithmetic and logic operations; DNA sequence alignment; cryptography; high speed memory interconnects

DDC classification:

621.3 KAV

Dissertation note: AI hardware accelerators Summary: This system level innovation is vital for supporting the high data rates required by modern artificial intelligence hardware accelerators ensuring communication between various components of a computer system.

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Item type	Current library	Collection	Call number	Status	Barcode
Theses and Dissertations	IIITDM Kancheepuram Library Theses and Dissertation	Theses and Dissertation	621.3 KAV (Browse shelf(Opens below))	Available	TD00605

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AI hardware accelerators

This system level innovation is vital for supporting the high data rates required by modern artificial intelligence hardware accelerators ensuring communication between various components of a computer system.

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